Increasing the ADC sample rate

Increasing the ADC sample rate

The code below increases the ADC sample rate from the standard value of 10 kHz up to 76 kHz, which allows you to read higher frequency signals.

// Put the two defines at the top of your code.

#define cbi(sfr, bit) (_SFR_BYTE(sfr) &= ~_BV(bit))
#define sbi(sfr, bit) (_SFR_BYTE(sfr) |= _BV(bit))

// Put this in your setup function somewhere.

  cbi(ADCSRA,ADPS0);
  cbi(ADCSRA,ADPS1);
  sbi(ADCSRA,ADPS2);

Another way of doing the same thing is like this:

  // Put this in your setup() function somewhere.
  
  // Increase the analog sample rate to 76 kHz.
  ADCSRA &= ~( _BV(ADPS0) | _BV(ADPS1) ); // clear bits 0 and 1.
  ADCSRA |= _BV(ADPS2); // set bit 2.

The way it works is that the clock which drives the ADC is driven from the main system clock with a prescaler which you can set yourself using the chip's registers. This example sets the prescaler to 16 (by setting ADPS2:0 in ADCSRA to binary 100), which gives a sample rate of 76 kHz. (The ADC takes 13 clock counts to make a reading). This is the highest value you can use without risking degrading the readings. Higher sample rates are possible, but the readings aren't so good according to the datasheet.